By Frank Schirrmeister
Full disclosure: I am writing this series in my role as program chair of the DAC Engineering Tracks, hoping to give you plenty of reasons to join us in Long Beach, not as part of my day job at Synopsys. The observations, the map, and any opinions are mine alone and do not represent my employer.
Every summer, the global semiconductor ecosystem converges for one week, transforming a single venue into the epicenter of technological progress. This year, the 63rd Design Automation Conference (DAC)—officially rebranded as "The Chips to Systems Conference"—descends upon Long Beach, California. As we prepare for this gathering, it is evident that we have reached a pivotal inflection point. The AI transformation of chip design, once a subject of abstract debate and skeptical side-eye, has moved off the analyst slides and onto the physical show floor.
The State of the Industry: From Band-Aids to Blueprints
To understand the current state of the industry, one must look to the perspectives of veterans like Simon Davidmann. A pioneer in simulation and verification, co-creator of SystemVerilog, and founder of Imperas, Davidmann has spent decades at the bleeding edge of EDA. His recent essays have framed a critical debate: Are we witnessing a true architectural reset, or simply a high-tech "band-aid"?
Davidmann argues that current agentic AI primarily automates workflows humans already perform—connecting existing tools via scripts and APIs. While useful and measurable, this approach remains tethered to human-shaped silos. The "magic," he posits, will only emerge when we adopt a holistic approach that rethinks the toolchain itself, allowing AI to reason across the entire stack rather than merely shuttling data between four decades of fragmented legacy tools.
Davidmann’s Dilemma and The Test
This tension is best captured by two concepts Davidmann has introduced: "Davidmann’s Dilemma" and "Davidmann’s Test."
The Dilemma is a systemic observation: everyone in the ecosystem acts rationally, yet the collective outcome is suboptimal. Incumbents protect their platform gravity; startups attack the most painful workflow bottlenecks; giant users like Samsung and Nvidia guard their IP behind firewalls; and academia optimizes for publishable, narrow benchmarks. Everyone is shoveling faster, but no one is changing the shape of the mountain.
Davidmann’s Test provides a yardstick for innovation: "Does it change what you can verify, or just how fast you run what you already verify?" If a solution only optimizes existing speed, it fails the test.
A Landscape of 130 Contributors: The DAC 2026 Stack
The DAC 2026 AI landscape can be visualized as a stack, read from the foundations upward. Understanding this hierarchy is essential for anyone walking the exhibit floor:
- Compute Infrastructure (Layer F): The bedrock of 31 companies providing the IP, foundries, chips, and systems that power the entire ecosystem.
- Design Data & Infrastructure (Layer E): Five companies managing IP lifecycles, MCP, and RAG servers, providing the context for AI agents.
- AI Models & Foundations (Layers A & B): Three frontier LLM providers and 10 custom domain model developers. This is where the battle for intelligence differentiation occurs.
- Classic EDA Tools (Layer G): 26 providers covering the five stages from idea to silicon.
- Agentic Point-Tool Enhancements (Layer D): 20 companies weaving AI into specific tool cockpits.
- Agentic AI Flows (Layer C): 22 companies orchestrating across tool boundaries.
- Developer Use Cases: The pinnacle of the stack, where the Engineering Track’s user experiences reside.
Alongside this stack, we find the "rails"—the security firms ensuring trust and the standards bodies like Accellera and Si2 that define the seams between layers.
The Mechanics of Autonomy: L1 to L5 and the ODD
Many vendors have adopted the SAE automation levels (L1–L5) from the automotive industry. However, in the context of chip design, the "level" of autonomy is only half the story. The missing half is the Operational Design Domain (ODD).
In self-driving cars, an L4 robotaxi is only L4 within a specific, geofenced urban environment. In EDA, the ODD is the scope of the design flow the AI touches. An L4 agent operating inside a single tool cockpit is Category D—high autonomy in a narrow, controlled domain. An L4 agent operating across the entire flow is Category C—a significantly more complex ODD because every boundary crossed introduces new failure modes. When you visit booths this year, the question should not be "What level are you?", but rather, "L4 within what ODD?"
Strategic Divergence: The Spectrum of Model Relationships
How deep does a company’s relationship with its AI model go? We are seeing a distinct split in the market:
- The Physics-Informed Extreme: Companies like Cognichip train their own models on governed, synthetic chip design data. Their philosophy: fine-tuning general-purpose models on internet-scale data is insufficient for the precision required in chip architecture.
- The Orchestration Extreme: Companies like MooresLabAI openly leverage frontier models (Azure OpenAI, AWS Anthropic), betting that their value-add is not the model itself, but the intelligent orchestration and wrapper logic.
Between these poles lie the "fine-tuners," companies adapting base models to domain-specific needs. Whether one wraps, fine-tunes, or trains from scratch, each strategy represents a different bet on where long-term value will accrue in the semiconductor supply chain.
Implications for the Future of Verification
The "Big Three" EDA vendors—Cadence, Synopsys, and Siemens—are working to weave agents into their platform gravity wells. Their goal is to ensure that "which model signs off your chip" resolves to "ours, inside our platform." This creates a powerful, integrated environment, but the industry must remain vigilant. If the platform becomes too closed, does it stifle the possibility of a genuine, transformative reset?
Conversely, the insurgent startups in Category C are providing much-needed friction. With companies like Bronco AI introducing production-grade benchmarks like DVBench, the industry is moving toward a more empirical way of measuring success. We are shifting from "demo-ware" to measurable ROI, which is exactly what is required to pass Davidmann’s Test.
A Call to Action for Attendees
The debate between the "band-aid" and the "reset" will not be settled in a single keynote. It will be decided in the hundreds of conversations held in Long Beach. DAC 2026 is the first conference where both approaches exist at production quality.
I encourage you to use the DAC Explorer tool to plan your journey. It acts as an Expedia for the conference, helping you map your interests to specific sessions. Attend the Pavilion discussions, such as "Agentic AI in EDA: Who’s in Control?" and the Wednesday Exhibitor Forum panel on SoC verification.
This is a year for intentional walking. Every booth you visit, every demo you watch, and every panel you attend should be filtered through the lens of the stack. Does this tool just make the shovel move faster, or is it fundamentally redesigning the mountain?
The future of chip design is being written in real-time, and it is being written by the engineers and visionaries gathering in Long Beach. I look forward to seeing you there, witnessing firsthand how the next generation of silicon is being architected—not just by human hands, but by the thoughtful, holistic application of artificial intelligence.
This is Part 1 of 3 of the DAC 2026 series. Part 2 will explore the Engineering Track’s user experiences and how companies are auditing vendor AI. Part 3 will focus on the sessions dedicated to the creation of the AI chips themselves. Registration is open at dac.com.
